Analog-to-Digital Conversion Expertise

We have leading expertise in designing ADCs:

  • Continuous Time ΣΔ ADCs 12-14bit 50 MS/s
              800MS/s – 1.2 GS/s Modulator – Industries lowest power ADCs!

  • Switch Cap Incremental ADCs up to 24bit, 100S/s
              Measurement Applications (e.g. MEMS Sensors)

  • SAR ADCs 8-12bit up to 10MS/s
              Tiny charge redistribution converters with ultra low power consumption

  • SAR ADCs 8-10bit up to 500MS/s
              High Speed & low power consumption

  • Switch Cap ΣΔ ADCs 16-18bit 96-192kS/s
               Audio Type Low Power converters SNR > 102dB, THD > 110dB


Continuous Time ΣΔ ADC

TODAY’S high-speed, high-resolution analog-to-digital conversion (ADC) is based on pipeline conversion technology. These Nyquist-rate ADCs are the core building blocks of analog front-ends. Significant effort has to be put into the signal conditioning preceding Nyquist-rate ADCs and the generation of both voltage and time references. Oversampling ADCs trade digital signal processing complexity for relaxed requirements on the analog components compared to Nyquist-rate ADCs. The popularity of continuous-time (CT) ADCs has been growing for application-specific ICs. Moreover, continuous-time implementation of ADCs extends the input frequency range from a few 100 kHz up to a few 10 MHz and proves to be very power efficient.

Owing to the non-sampling input stage (sampling takes place after the continuous-time loop filter), continuous-time ΣΔ ADCs exhibit an inherent anti-alias filter function, enabling the design of alias-free ADCs. Thus, high-order anti-alias filters, which are either power-hungry in the case of active filters or occupy considerable board space in the case of highly linear passive filters, can be avoided. These unique features are particularly important for mobile applications (e.g., wireless, instrumentation and measurement), since these are battery powered and limited in available space.

Continuous Time ΣΔ Modulator

A 20mW 640MHz CMOS first CTΣΔ ADC with 20MHz Signal Bandwidth

Key Features:

  • Supply Voltage 1.2V
  • Clock Frequency 640MHz
  • DNR = 80dB, THD < -78dB
  • ENOB = 12b, SNDR= 76dB
  • 14-bit 20-40 MS/S Decimated Output Data
  • Power Consumption 20mW

Mismatch Calibration of

  • Quantizer 4bit – 640MS/s
  • DAC SNR 80dB – 640MS/s
  • back ground calibration!


System Simulation


Alias free sampling

Aligning of Digital and Analog transfer functions => No/little Aliasing!


Inherent Anti-aliasing Transfer Function of a CTDS Architecture


Transfer Function of Decimator Filter & CTSD Modulator combined



FFT Plot of Measured ADC Output Data of 32kSamples at 40MS/s


SAR Charge Redistribution ADCs

The AA successive approximation register (SAR) ADC family are charge redistribution based successive-approximation analog-to-digital converters. The SAR ADCs are composed of an n-bit DAC, auto-zeroing comparator, reference buffer and a digital control unit. One of the major benefits of the SAR-ADC converters are the integrated error correction logic enabling the converters to correct false analog comparisons, making the ADC very robust against supply and substrate noise, and glitches within the application.

Some AA-SAR ADCs comprise an input multiplexer, switching up to 8 external inputs to the ADC input. With this functionality, 2 channels can be simultaneously sampled (equivalent to having 2 sample and hold functions), making it therefore ideal for multi signal measurements and comparisons.

Simultaneous sampling of 2 Channels (I/Q)

Key Features:

  • 10bit up to 220kS/s
  • 1.8V Single Supply
  • Simultaneous sampling of 2 Channels; e.g. IQ Processing
  • up to 6 (single-ended) Input Channels
  • 0 – 2V Input Voltage Range
  • Internal Reference Buffer
  • Effective Number of bits 9.3
    DNL < ½ LSB
    INL < ½ LSB
    No Missing Code
  • Digital Adjustable Parameters
    Input Range +/- 200mV
    Gain Adjust +/- 5%
  • Low power Consumption
    <350µW @ 1.8V Supply & 2CH
  • Small Foot-Print 0.2 mm2
    at 180nm CMOS
  • Extensive Characterization & Production (ATE) Test Features
  • Silicon Proven!


Shuffling of DAC Elements

Shuffling attenuates impact of gradients by 70dB!


Full Scale Ramp Signal applied to 2 Channels

Output of both Channels are plotted in one graph


Data Capture of Full Scale Sine Wave at 2 Channels

2Vpp sine wave @ 250Hz +1.2V DC


FFT of ADC output data
Input Signal: 2Vpp sine wave @ 5kHz + 1.2V DC


INL & DNL Performance

INL< +/-0.3LSB   DNL < +/- 0.2LSB


SNR, SNDR vs. Supply Voltage


High Speed SAR ADCs

A 250MS/s 9bit SAR ADC comprising 4 interleaved SAR ADCs 

Key Features:

  • Supply Voltage 1.2V
  • Input Voltage Range 1Vppdiff
  • Clock Frequency 250MHz
  • SNR = 52dB, SFDR > 64dB
  • DNL <±½LSB, INL <±½LSB
  • ENOB = 8.2b
  • Silicon Proven Architecture!


SAR ADC Architecture


Settling requirements τ


ADC Clock Specification Aperture – Jitter


20150901 Aperture Jitter

SNR Performance Limits due to Clock Jitter


Signal Processing close to large Carrier


Signal Processing close to Carrier

ADC output spectrum


PLL Specification for Close-in Phase Noise