Clock Generator & Synthesizer Expertise

We have leading expertise in designing clock generators & synthesizer :

  • Fractional Phase Lock Loops (PLLs) with Low Jitter in combination with a large Tuning Range

  • Integer (LC) PLLs with Ultra Low Jitter (< 100fsrms!) in combination with a large (>1GHz) Tuning Rang

  • DLLs with large Tuning Range to generate clock phases (for e.g. SAR ADCs)


Clock generators & Synthesizer are essential for modern communication and high-frequency data-conversion (ADCs & DACs) applications, since its jitter performance directly impacts the overall system performance.

In addition to be a frequency multiplier (of external lower frequency clock) an on-chip clock generator should ease the system and board level requirements associated with high performance clocking & sampling.


A fourth order charge pump PLL with passive loop filter and a LC-VCO

The core of the PLL is a oscillator with a sophisticated tank circuitry comprising inductors, capacitors and varactors, enabling ultra low clock jitter performance (tj<400fs rms) while providing a huge tuning range (~1GHz). The wide tuning range is achieved by means of a digital coarse and analog fine tuning algorithm implemented within the PLL. The control logic continuously monitors lock-status and may initiate a self-calibration. The PLL is specified from a temperature range of TJ -40°C to +125°C.

Key Features:

  • Singles Supply Voltage 1.2V
  • Input Capture Range 13.5MHz-40MHz
  • Output Clock 432-640MHz
  • 1.7GHz– 2.56 GHz LC-VCO
  • Phase Noise < 115dB@400KHz
  • JitterPS < 400fsrms1), BW=400kHz
  • Power Consumption 12mW@2.56GHz
  • 130nm CMOS

1) see Jitter definitions at the end of the page


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Layout of LC VCO 1.728 -2.56GHz

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PLL Measurement Results
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PLL Phase Noise

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PLL Phase Noise measurements by analyzing the Output Data of the clocked ADC

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A Universal Low Power 1GHz PLL

Key Features:

  • Wide Input & Output Frequency Range
    fin=1MHz -100MHz, fout=10MHz-1GHz
  • 1.8V Single Supply
  • 180nm CMOS
    NO analog Process Option!
  • JitterPS <21psrms1)
  • No Biasing & References required
  • Programmable Pre-, Post- and Feedback Divider
  • Low power Consumption max. < 2.8mW @ 1.8V Supply
  • Small Foot-Print 0.04 mm2
  • Silicon Proven Architecture!

1) see Jitter definitions at the end of the page


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Programmable parameters
  • VCO center frequency: 800MHz
  • VCO maximum operating frequency 1GHz
  • Pre-divider division 4b: m <1…15> with 50% duty cycle
  • Post-divider division 5b: n <1…31> with 50% duty cycle
  • Feedback division 8b: N <1…255> with 50% duty cycle
  • Programmable Loop bandwidth

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Examples of supported Input and output frequencies

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PLL System Simulations

PLL Transfer Functions

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PLL Phase Noise Transfer Functions

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PLL Noise Shaping

PLL pnoise below 500MHz carrier – w/o input clk noise

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PLL Jitter Measurement

Phase Noise Measurement with R&S FSUP

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Measurement: VCO frequency (MHz) vs VTUNE (V)
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Measurement: IDD (mA) vs VCO frequency (MHz)

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Layout of the Universal 1GHz PLL
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Jitter Definitions

The RMS value of the (Phase Noise) Jitter is the phase fluctuation’s RMS over the specified frequency range, scaled by 1/(2πfo):

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Time domain Instruments (TDI)

TDIs have many options for measuring jitter

A popular measure is the Period Jitter.

  • Period jitter compares the length of each period to the average period of the clock

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The Period Jitter is related to the Phase Noise spectral density by the following integral relationship

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Relationship between Period Jitter & Phase Noise

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